1. Field of the Invention
The invention relates in general to a computer-implemented method for generating placements for integrated circuits (ICs) and, in particular, to a method for generating placements for analog ICs using constraint trees.
2. Description of the Prior Art
In modern IC industry, analog ICs gain more and more importance. An analog IC is described by a netlist which includes a set of interconnected device modules such as transistors, capacitors, resisters and other devices. The functionality and performance of the analog ICs are heavily influenced by the placement of the device modules of the circuits. A computer-implemented placement tool processes a netlist to determine a suitable position and orientation for each of the device modules within the IC. To guarantee a correct functionality and best performance for the analog ICs, a set of constraints are provided for placing the device modules.
For example, “symmetry constraint” is introduced to reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations. According to the symmetry constraint, two device modules are placed symmetrically with respect to a common axis. Symmetry constraints are typically categorized into three types. The first type is horizontal one-dimensional symmetry constraint; the second type is vertical one-dimensional symmetry constraint; and the third type is two-dimensional symmetry constraint.
Another example is “proximity constraint” or “cluster constraint” which limits a particular group of devices placed near one another so that they can be interconnected by short wires.
Another common example of constraints is “matching constraint” which specifies a pre-defined matching placement pattern for a circuit. For instance, a current mirror circuit comprises two transistors which should be tightly coupled with a specific gate orientation. Other constraints such as spacing, boundary, clearance, etc., are also well-known and commonly used in analog IC placement.
U.S. Pat. No. 7,873,928 entitled “Hierarchical Analog IC Placement Subject to Symmetry, Matching and Proximity Constraints” discloses a method of defining a multiple-level hierarchy of constraint groups and generating an optimal placement. However, the proposed approach assumes that all the constraints are self-contained and does not mention how to deal with constraint conflicts.
FIG. 1 depicts a block diagram which illustrates a general concept of a prior approach in how to handle constraints. Block 11 represents a set of constraints for an IC design. The constraints 11 are directly saved into a constraint database 12 without any additional checking. A placer 13 refers to the constraint database 12 and tries to find placements that satisfy all the constraints in the constraint database 12.
However, constraints can conflict with each other. It means that two constraints cannot be satisfied at the same time. Thus all the placer 13 can do is trying to satisfy as many constraints as possible without analyzing the conflicts in a systematical way.
Therefore, what is needed is a systematic approach to analyze an IC design and its corresponding constraints. In addition, the analysis result should be able to detect and resolve conflicts of constraints. Furthermore, it is desired to find a systematic approach to generate placements for the IC design while meeting all the constraints based on the analysis result.